1. Field of the Invention
The present invention relates to the field of integrated circuits and high-speed buses. More specifically, the present invention relates to a circuit for a high-speed driver and techniques for obtaining rapid switching speed with low power consumption and low noise on high-speed buses.
2. Description of the Related Art
To obtain rapid switching speed on a bus with low power consumption and low noise, it is desirable for a current mode driver to set and control the current at which the driver operates. U.S. Pat. No. 5,254,883, assigned to the assignee of the present invention, and incorporated herein by reference, discusses an apparatus and method for setting and maintaining the operating current of a current mode driver for a bus. Essentially, for a bus with a master-slave architecture, there are two problems to be solved in setting the operating current on the bus. First, the operating current of the master""s current mode drivers should be properly set. Second, the operating current of the slave""s current mode drivers should be properly set. Once these currents are set, they are maintained at those settings despite process, voltage and temperature variations by circuitry in the master and slave devices.
A master-slave bus architecture is discussed in the ""883 patent in which a master may send data to and receive data from a slave. A slave may send data to and receive data from a master, but not another slave. The master sets its operating current for its drivers and each slave sets the operating current for its drivers.
The master employs an adjustable current sink as a driver for each bus line that it drives. The current sink turns or to drive the voltage on the bus line, Vout, to a voltage closer to ground and turns off to allow a termination resistor, Rterm, on the bus line to pull the bus line closer to the terminator voltage, Vterm. The current in the driver, Id, is set by a digital counter whose count is determined from a feedback circuit having a comparator. If the count is all zeros then no current flows in the driver and the voltage on the bus line, Vout, is the termination voltage, Vterm. If the count is all ones, then the maximum current flows in the driver and the voltage on the bus line, Vout, equals Vtermxe2x88x92Id*Rterm.
The feedback circuit compares a voltage reference, Vref, to a node voltage, Vn, derived from a scaled reference driver which receives the count from the counter. Feedback assures that the node voltage matches the reference voltage, Vn=Vref, When the match occurs the reference driver has an output swing (i.e., change in voltage) of (Vtermxe2x88x92Vref) and the actual output driver has a swing of 2*(Vtermxe2x88x92Vref) due to the scaling between the reference driver and the actual output driver. Therefore, Vout equals (Vtermxe2x88x922)*(Vtermxe2x88x92Vref). Thus, by selecting a value for Vterm and Vref any size symmetric voltage swing about Vref may be achieved.
The slave in the ""883 patent also employs an adjustable current sink as a driver for each bus line that it drives. A counter similarly controls the value of the current in the driver such that the driver may swing between Vterm and Vtermxe2x88x92Id*Rterm, where Id is the current setting in the driver of the slave. However, the value in the counter is directly proportional to the value of an RC time constant whose capacitance, C, is set by the master. The master also determines whether the value of Vout from the driver matches Vref in the master. It adjusts the RC time constant so that the count in the counter will set a current in the driver and Vout will match Vref. Thus Vout will equal Vtermxe2x88x92(Vtermxe2x88x92Vref). In order to produce a symmetric swing about Vref another step is required. The master should double the value of the RC time constant which will double the count. This will produce a Vout which is equal to Vtermxe2x88x922*(Vtermxe2x88x92Vref).
Maintenance of the current setting of the driver in the slave may be performed in a manner different from that in the master. In the slave, the effective R in the RC time constant is derived from a reference voltage and reference current. If due to variations in temperature or supply voltage, the reference current decreases then the effective R in the RC time constant increases. This increases the count and the operational current setting of the driver in the slave, thus compensating for the effect. If the reference current increases, the effective R and the count decrease, again compensating for the change.
While the above techniques of setting and maintaining operating current in the master and slave bus line drives have met with substantial success, the techniques are not without certain shortcomings. For example, the technique of setting the current in the master requires an extra pin dedicated to receive the external resistor. Another shortcoming is selecting the proper value of the external resistor to maintain the factor of two scaling between (Vtermxe2x88x92Vn) and (Vtermxe2x88x92Vout). If the scaling is not precisely set, the output swing is not symmetric about Vref, Further, as process, voltage, or temperature variations occur, the value selected for the resistor may not be ideal. A further shortcoming is that an electrostatic discharge structure (ESD): in series with the pin receiving the external resistor adds a variable amount of resistance in series with the external resistor. This makes the selection of the external resistance subject to variations in the ESD structure.
Further, a shortcoming in the technique of setting the current in the slave is that a relatively complex algorithin between the slave and the master is required to correctly set the current in the slave. The master sets the RC time constant which in turn determines the count and the output value. The master then tests the output value to determine whether it matches Vref. If not, it increases the count and retests the output value. This cycle continues until a match occurs. However, a match of Vout to Vref for one bus line, does not always insure that a match will occur on another bus line due to small differences in characteristics between output drivers, bus lines, and Vref comparison circuits.
As can be seen, an improved output driver circuit and techniques for obtaining rapid switching speed with low power consumption and low noise is needed.
The present invention includes a circuit and current control technique to enable high-speed buses with low noise. This circuitry may be used in the interfacing of high-speed dynamic RAMs (DRAMs). The architecture of the present invention includes the following components: an input isolation block (Isolation), an analog voltage divider (AVD), an input comparator, a sampling latch, a current control counter, and a bitwise output driver (output driver A and output driver B).
A fundamental operation of the current control mechanism is to evaluate the voltage levels Vhi, Vlow, and Vref, and increment or decrement the current control counter accordingly to set an appropriate output level. When the current control circuitry is in an evaluation mode, output driver A is off (not sinking current), and node BDA is at the output high voltage level (typically Vterm). Output driver B is active, and pulls node BDB to the low voltage output level. The voltage levels at nodes BDA and BDB are passed through the isolation block, and fed into the analog voltage divider. The analog voltage divider outputs a voltage level which is a weighted average of it""s input. I.e., Vout=(A*hi)+(B*Vlow). For example, in a specific case, Vout=(0.5*Vhi)+(0.5*Vlow).
The input comparator compares Vout and Vref and generates an up signal. The up signal is sampled, and used to increment or decrement the current control value held in the current control counter. By repeating this process the current control value will settle to a value where Vol=(Vrefxe2x88x92A*Vterm)/B.
When the current control circuity is not active, the input isolation block shields any interactions of the analog voltage divider circuitry and the output pad.
The output driver is composed of a series of individual output transistors, an example of which is shown in FIG. 4. The number of active output transistor blocks are selected with control signal ictrl[n:O]. The width of the output devices may be scaled in a geometric fashion to allow encoding of the ictrl[n:O] signal.
The input isolation gates may be implemented as CMOS pass gates, NMOS passgates with boosted gate voltages, unity gain buffers, or operational amplifiers (op amps). The analog voltage divider may be implemented with a resistor divider, a digital-to-analog converter, or switched capacitor filter such as a sigma/delta modulator. The sampling latch may be implemented as a simple flip-flop or latch, or a series of sequential elements with logic to average the sampled value. The current control counter may be implemented as an up-down counter or a more sophisticated counter such as a saturating binary search counter.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.